In designing circuit components for telecommunications systems, such as, for example, a 1603 SM Add/Drop Multiplexer subsystem manufactured by Alcatel Network Systems for use in a Synchronous Optical Network (SONET) system, a primary goal has been to minimize the subsystem's size, complexity and power consumption while maximizing its signal transport capabilities and operational performance. However, increased customer intolerance of interrupted service has shifted a significant amount of design emphasis to increased survivability of the overall system. Consequently, increased design emphasis is being given to early recognition of degraded or interrupted signals and responsive, automatic rerouting of traffic over redundant or standby circuitry.
In designing logic circuits for high speed telecommunications systems, such as, for example, a CLK 101 clock circuit card for a 1603 SM Add/Drop Multiplexer, it is most advantageous to convert incoming ECL-balanced digital signals (e.g., a DS2 signal and its complement) to CMOS level signals to minimize power consumption, and effect an efficient interface between the two signal levels to maximize switching speed. For example, as illustrated in FIG. 1, a conventional technique uses a type 10H125 ECL-to-TTL converter chip manufactured by Motorola to convert an incoming ECL-balanced signal to a TTL level signal, which is then input to an ACT 74 CMOS logic stage manufactured by Motorola. However, this technique is relatively limited and inefficient, because the 10H125 chips perform adequately only as an interface stage between ECL logic and TTL or "ACT" type CMOS logic gates, but inadequately as an interface with standard CMOS logic gates (e.g., "AC" CMOS gates) or Application Specific Integrated Circuits (ASICs) having CMOS level input stages.
Also illustrated in FIG. 1 is a conventional use of toggle-fault detection circuitry to help increase the survivability of the overall telecommunications system. Generally, the toggle-fault detection circuitry generates an alarm signal when one or both of the digital input signals is significantly degraded or missing altogether. Typically, when both digital signals input on lines l1 and l2 are "toggling" (i.e., switching properly between logic state "1" and "0"), this condition is defined as "full toggling" and no "toggle-fault" alarm signal is required to be generated. However, if either of the digital input signals is "stuck" at logic "1" or "0" ("half-toggling" condition), or both input signals are "stuck" ("non-toggling" condition), then a toggle-fault alarm signal is generated. In response to this alarm signal, the system is designed to reroute signal traffic to a backup or standby circuit card. Specifically, referring to FIG. 1, each of the digital signals input to converter circuit 100 is coupled to an input connection of ECL to TTL converter 110. One input signal is also coupled to an input connection of ECL to TTL converter 130, while the other signal is coupled to the complementary input connection of ECL to TTL converter 140. If one or both of the input lines fails to "toggle" then the signal degradation is accompanied by a decreased output signal from respective converter 130 or 140, or both. A signal decrease at output connection Q2 of converter 130 is detected by clock detection circuit 152, and a signal decrease at output connection Q3 of converter 140 is detected by clock detection circuit 154. Accordingly, a toggle-fault alarm signal is output from a respective clock detection circuit to microprocessor 160, in response to a half-toggle or non-toggle condition detected on the input lines to circuit 100. In response to such an alarm signal, microprocessor 160 generates control signals that are coupled to switching circuits (not explicitly shown), which operate to reroute the signal traffic to bypass the faulty card, and thereby minimize system downtime.
FIG. 2 shows the details of clock detection circuits 152 and 154 of FIG. 1. As illustrated by FIG. 2, a major disadvantage of converter circuit 100 is that a significant number of ("ACT") CMOS gates must be used to provide toggle-fault detection. Since the power consumption of these types of logic gates increases with processing speed, they increase the power consumption of circuit 100 significantly (about 100 to 200 mwatts) because they are toggling at the relatively high rate of 52 Mbits/sec. Also, the use of 10H125 type chips for converters 130 and 140 results in an additional power consumption of about 300-500 mwatts for converter circuit 100.
FIG. 3 illustrates a second conventional technique that is used to convert ECL-balanced signals to CMOS level signals, which also includes toggle-fault detection. Essentially, the signal on each line l1 and l2, input to converter circuit 300 is monitored by an AC-coupled peak detector. A toggle-fault alarm signal is output from either of amplifiers 330 or 340 in a respective detector circuit, if either one of the input lines fails to "toggle" or the "toggling" action of one line is faulty. However, since the ECL signals being monitored on lines l1 and l2 are only approximately 0.8 V p--p, the use of diodes to detect and bias such relatively small signals in such a circuit arrangement is a technique that is extremely sensitive to temperature variations. For example, the forward drop for any diode in circuit 300 can vary up to +/-150 mV as a function of temperature. Therefore, it is extremely difficult to achieve optimum performance of converter circuit 300 over a full range of operating temperatures between -40.degree. C. to 85.degree. C. Furthermore, the relatively high number of discrete components being used for toggle-fault detection adds a substantial amount of power consumption for circuit 300.